A contemporary hearing aid comprises electronic circuits of very large scale integration in order to accommodate the circuits necessary to perform the desired functionality of the hearing aid while keeping the physical size of the hearing aid as small as possible. This means that the chip or die containing the semiconductor components of the hearing aid also has to be as small as possible in order to fit within the hearing aid housing. At the same time the circuit needs to be optimized to use as little power as possible in order to prolong the life of the battery powering the hearing aid.
Due to a number of practical issues, it is often necessary to distribute the circuit on several silicon dies and provide interconnections between the parts of the circuit residing on different silicon dies or chips, e.g. in the form of bonded electrical connections from one chip to another. Interface terminations for these bondings are provided on each chip as larger, metalized areas denoted pads. During assembly, the pads of different chips on the same substrate are interconnected by bonding wires, e.g. by soldering or ultrasound-welding the bonding wires to the pads forming electrical connections between the wire ends and the pads. The wires and the pads used in the assembly process are usually made from gold or other noble metals resistant to corrosion. Transferring digital signals reliably between individual chips usually consumes a lot of power on the chip, mainly because of the parasitic capacitance introduced by the interfacing pads and the associated components and connections. Since the semiconductor elements present on the chips are typically MOSFET transistors sensitive to electrostatic discharges (ESD), the inclusion of special ESD protection circuits are also mandatory when connecting chips to other chips or to peripheral components. However, the ESD protection circuits also contribute to the parasitic capacitance of the interface pad circuit.